1. Field of the Invention
The present invention relates to a driving circuit for N-type field effect transistors (FETs) suitably connected to a positive electrode side of a power supply circuit.
2. Description of the Related Art
In recent years, a secondary battery cell has been widely used for a power supply of an electronic appliance such as a note-type personal computer or a cellular phone. A protecting circuit is disposed in a secondary battery cell to prevent it from deteriorating and heating due to overcharging and over-current in a charging state and to prevent it from burning a current path due to over-current and deteriorating due to over-current in a discharging state.
For the protecting circuit, a P-type FET is used, although it is inferior to an N-type FET in characteristics because the former can be more easily controlled when it is disposed on the positive electrode side of the power supply than the latter.
As shown in FIG. 1, a discharge-control P-type FET 142 and a charge-control P-type FET 144 are disposed on a positive electrode side of a secondary battery cell 141. An NPN-type transistor 143 is connected to a gate of the FET 142 and a negative electrode side of the secondary battery cell 141. An NPN-type transistor 145 is connected to a gate of the FET 144 and the negative electrode side of the secondary battery cell 141. Bases of the transistor 143 and a transistor 145 are connected to a driving circuit 146. In such a manner, P-type FETs are used as a protecting circuit of a secondary battery cell.
A P-type FET is controlled by applying a voltage that is lower than the source voltage to the gate. In contrast, an N-type FET is controlled by applying a voltage that is higher than the source voltage to the gate. Thus, when an N-type FET that is superior to a P-type FET in characteristics is disposed to the positive electrode side of a secondary battery cell, a gate voltage necessary for controlling the N-type FET is generated by a charge pump so as to raise the battery voltage (refer to Patent Related Art Reference 1).
[Patent Related Art Reference 1] Japanese Patent Laid-Open Publication No. 2003-079058
As shown in FIG. 2, a discharge-control N-type FET 152 and a charge control N-type FET 154 are disposed on a positive electrode side of a secondary battery cell 141. A gate of the FET 152 is connected to a positive electrode side of a voltage source 156 through a resistor 153. A gate of the FET 154 is connected to the positive electrode side of the voltage source 156 through a resistor 155. A negative electrode side of the voltage source 156 is connected to a connection point of the FETs 152 and 154. The voltage source 156 is controlled by a charge-pump controlling circuit 157 that is controlled by a controlling circuit 158. In such a manner, N-type FETs are used as a protecting circuit of a secondary battery cell.
However, when the FET 152 and the FET 154 are controlled with the charge-pump circuit, the capacitance between the gate and the source of each of the FET 152 and the FET 154 becomes large. In other words, so-called virtual capacitors are formed. Thus, when the FET 152 and the FET 154 are used as switching circuits, their switching speeds become slow.
When the FET 152 and the FET 154 are turned off, electric charges stored in their virtual capacitors are discharged through the resistors 153 and 155. Thus, as shown in FIG. 3, gate voltages of the FETs 152 and 154 have their active periods. In other words, powers are generated temporarily in the FETs 152 and 154.
As shown in FIG. 4, a charge pump circuit 171 is composed of switching circuits 172, 174, 175, and 176, and a capacitor 173. The charge pump circuit 171 is controlled by a controlling circuit 168.
At that point, when the FETs 152 and 154 are turned off, after electric charges stored in the capacitor 173 are discharged to a resistor 177, gate voltages of the FETs 152 and 154 have their active periods as shown in FIG. 3. As described above, electric charges stored in the capacitor 173 are discharged by the resistor 177. Thus, powers are temporarily applied to the gates of the FETs 152 and 154. Consequently, switching operations for the FETs 152 and 154 become slow.